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Potential and challenges in gallium oxide,next gen power semiconductor tech

October 29 @ 6:30 pm - 8:00 pm PDT

San Francisco, & Oakland/East Bay Chapter of IEEE Power Electronics Society is excited to be back with the next in-person event

The SFBAC (combined Santa Clara Valley, San Francisco, & Oakland/East Bay) IEEE Power Electronics Society (PELS) is very pleased to invite you to our upcoming in-person event. We are excited and honored to have Prof. Uttam Singisetti of the University at Buffalo to speak on the topic ofPotential and challenges in gallium oxide, the next generation power semiconductor technologyon October 29, 2024 at Plug and Play Tech Center in Sunnyvale in the Silicon Valley Room.

Doors will open at 6:30pm; the seminar will start at 7:00pm. Snacks and refreshments will be provided free of charge to all attendees.

Registration is $5, payable at the door with the exception for current students who must register with their *.edu emails. You may register ahead of time without paying, but ALL ATTENDEES (except for students) will need to pay at the door.

SFBAC PELS WEBSITE LINK: https://r6.ieee.org/scv-pels/

Seminar Title:

Potential and challenges in gallium oxide, the next generation power semiconductor technology

Abstract:

The monoclinic -gallium oxide (Ga2O3) (bandgap 4.8 eV) is one of several ultra-
widebandgap semiconductors (UWBGs) that have garnered a lot of interest as next generation power semiconductor technology. Since the first demonstration of a MESFET in 2012, Ga2O3 device research has progressed at an incredible pace with reports of MOSFETs and diodes achieving 10 kV breakdown voltages. Gallium oxide devices have also achieved impressive high power device figure of merit, high average field strengths and high-speed performance. The high critical electric field, good electron mobility, multiple shallow donors, availability of large area substrates and growth of high-quality epitaxial films; have all contributed to the rapid progress in device performance. As a result, it has emerged as a promising ultra- widebandgap semiconductor for next generation power, GHz switching and RF applications. In addition to the large Baliga’s Figure of Merit (BFoM); good electron mobility, calculated electron velocities lead to higher Johnston’s Figures of Merit (JFoM). Additionally, the large bandgap also enables high temperature operation and radiation hardness making it attractive for space applications such as Mars and Venus missions. This talk will present the most recent advances in gallium oxide devices; both from our group and others. We will present the lateral MOSFETs with improved field plate design and beyond-kV
breakdown. Temperature dependent analysis and device simulation suggest an extrinsic breakdown mechanism outside the channel. A simple and yet effective SU-8 polymer passivation technology provides a significant improvement in breakdown voltages. The higher field strength of the SU-8 polymer enables a significant increase in breakdown voltage to 8.5 kV in lateral MOSFETs. However, these devices show a high Ron, which is due to the depletion caused by RIE of the channel. We will present the use of ultra-high vacuum annealing techniques to improve the on-resistance of the devices still maintaining the multi-kilo-volt rating of the devices. We will also present on-wafer individual device level switching characteristics. I will discuss the progress made on vertical Schottky barrier diodes (SBDs) which have rapidly achieved both high voltages and high-power deice figures of merit. Several groups have incorporated nickel-oxide/gallium oxide hetero-junction p-n diodes to successfully overcome the absence of p-doping in gallium oxide. High surge-current capability and unclamped inductive switching (UIS) have been demonstrated in these devices despite the low thermal conductivity. Finally, I will discuss the approaches that could address the challenges in this semiconductor system (low thermal conductivity and absence of p-doping). I will conclude by discussing the factors that could potentially lead to successful lab-to-fab transition in this exciting next generation power semiconductor technology.

About the speaker:

Dr. Uttam Singisetti is a Professor of Electrical Engineering (EE) at the University at Buffalo (UB). He received his PhD in Electrical and Computer Engineering from the University of California, Santa Barbara in 2009. He received MS degree from Arizona State University in 2004 and BS degree from the Indian Institute of Technology, Madras in 2001. He joined the EE department at UB in Fall 2011 and was promoted to Associate Professor in 2017 and full Professor in 2021. His research interests are in the areas of low-power devices for logic and memory; III-N based THz devices and next generation wide and ultra-wide bandgap materials and devices. He was the first to demonstrate high frequency enhancement mode devices in the N-polar GaN technology. During his Ph.D. he worked on III-V MOSFET devices, where he demonstrated a fully self-aligned III-V MOSFET technology. At UB, Singisetti has conducted seminal work on Ga2O3 devices and materials in the last few years. He conducted pioneering fundamental work inunderstanding the low field and high field transport in Ga2O3 that has led to great insights into the electron dynamics in this semiconductor. His research group was the first to identify the mobility limiting mechanism in Ga2O3, demonstrated multi-kV-class lateral Ga2O3 devices, and highest RF performance in scaled Ga2O3 devices. He is recipient of Senior Researcher of the Year (2019-2020) award and UB Exceptional Scholar: Sustained Achievement Award in 2024. He has co-authored more than 150 publications in peer reviewed journals and conference proceedings with > 4400 citations. He is a Senior Member of the IEEE Electron Device Society. He served on the technical program committee of the IEEE Device Research Conference and on the IEEE EDS Technical Committee on Compound Semiconductor Devices and Circuits. He was Chair of a successful GOX2023 conference in 2023. He has served as Guest Editors in several journals including IEEE Transactions on Power Electronics, Scientific Reports and APL Materials.

Venue

Plug and Play Tech Center/Silicon Valley Conference Room
440 North Wolfe Road
Sunnyvale, CA 94085 United States

Organizer

IEEE SFBAC PELS

Venue

Plug and Play Tech Center/Silicon Valley Conference Room
440 North Wolfe Road
Sunnyvale, CA 94085 United States

Organizer

IEEE SFBAC PELS