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DTSTART;TZID=America/Los_Angeles:20250219T080000
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UID:64370-1739952000-1740157200@svec.org
SUMMARY:Eighth Annual Symposium on Heterogeneous Integration Roadmap and Annual Meeting
DESCRIPTION:Future Vision for Heterogeneous Integration from Global Perspectives\, 3 days\, keynote talks\, working groups …\nRegistration is $140 ($115 for IEEE members). PayPal is the credit card payments processor; please do not use your Paypal account during the payment process here.\nWhen you get to the Visitor Parking area\, staff will guide you to available section\, and to the South Tower to check in and get your badge.\nSpeaker(s): \, \, \,\nAgenda:\nCheck (https://eps.ieee.org/technology/heterogeneous-integration-roadmap/annual-hir-conference.html) FOR LATEST UPDATES and speaker bios.\nDay 1 – Wednesday February 19\, 2025\nForum on AI & Energy Efficiency and Advanced Packaging Metrology\n9:00 am – 10:30 am Data Center AI & Energy Efficiency Forum Srilatha Manne (AMD)\, Arman Shehabi(LBL)\, Moderator: John Shalf\n10:30 am – 10:40 am coffee & tea break\n10:40 am – 12:10 pm Adv Packaging Metrology: NIST Metrology Team Paul Hale & Antara Nandi\, Moderator: Bill Chen\n12:10 pm – 1:10 pm Lunch\n1:10 pm – 1:30 pm Welcome & Agenda Review\n1:30 pm – 2:15 pm Ramune Nagisetty (NATCAST )\n2:15 pm – 2:50 pm George Orji (NIST) Keynote\n2:50 pm – 3:25 pm Henning Braunisch (SMART USA)\n3:25 pm – 4:00 pm Christopher Bailey – ASU Initiatives 4:00 pm – 4:35 pm Raj Jammy (IMEC USA)\n4:35 pm – 5:30 pm Wine Tasting Reception\nDay 2 – Thursday February 20\, 2025\n9:00 am – 9:05 am Welcome\n9:05 am – 9:30 am HIR Vision\n9:30 am – 10:05 am Dae-Woo Kim (Samsung Electronics\, South Korea)\n10:05 am – 10:40 am Madhavan Swaminathan (PSU) 10:40 am – 10:50 am Coffee & Tea Break\n10:50 am – 11:25 am Albert Heuberger (Fraunhofer Microelectronics Group)\n11:25 am – 12:00 pm Jimmy Lu (ITRI ERSO Taiwan)\n12:00 pm – 1:00 pm Lunch\n1:00 pm – 1:10 pm Contribution Recognition – Plaque Presentation\n1:10 pm – 3:00 pm TWG Collaboration Meeting Team 1\n3:00 pm – 3:05 pm Coffee & Tea Break\n3:05 pm – 5:00 pm TWG Collaboration Meeting Team 2\n5:00 pm – 6:00 pm Wine Tasting Reception\nDay 3 – Friday February 21\, 2025\n9:00 am – 9:10 am Welcome and Agenda Review\, Hualiang Shi\, EPS SCV Chapter Chair\n9:10 am – 9:45 am Prith Banerjee (ANSYS)\n9:45 am – 10:20 am TBD\n10:20 am – 10:30 am Coffee Break\n10:30 am – 11:05 am Srinivas Vempati (Institute of Microelectronics -IME\, Singapore)\n11:05 am – 11:40 am Subramanian Iyer (UCLA) – "AePeX America – Implementing Strategic Directions for the US Electronics Packaging Industry"\n11:40 am – 12:40 am Lunch\n12:40 pm – 2:30 pm TWG Collaboration Meeting Team 3\n2:30 pm – 2:40 pm Coffee & Tea Break\n2:40 pm – 4:30 pm TWG Collaboration Meeting Team4\n4:30 pm – 4:45 pm Conference Wrap up\nSamsung Electronics Campus\, 3655 N First Street\, San Jose\, California\, United States\, 95134
URL:https://svec.org/event/eighth-annual-symposium-on-heterogeneous-integration-roadmap-and-annual-meeting/
LOCATION:Samsung Electronics Campus\, 3655 N First Street\, San Jose\, California\, United States\, 95134
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DTSTART;TZID=America/Los_Angeles:20250221T160000
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DTSTAMP:20260420T022151
CREATED:20250207T074809Z
LAST-MODIFIED:20250207T074809Z
UID:65623-1740153600-1740160800@svec.org
SUMMARY:Title: Trend and Opportunities for High-Speed (GS/s) ADCs
DESCRIPTION:Title: Trend and Opportunies for High-Speed (GS/s) ADCs\nAbstract: Analog to digital converter (ADC) is a critical building block for most electronic systems. Many\nwideband electronic systems (such as wireless and wireline communications) favor digitization of analog\nsignal with increasing bandwidth (>GHz) and fidelity; at the same time\, demand a low area/power\nconsumption. It leads to a great interest in high-speed ADCs in recent years. In this talk\, I will describe\nthe recent trend of high-speed (>GS/s) ADC. Many existing works leverage massively interleaved SAR\nADCs. On the other hand\, there are emerging opportunities to quantize the analog signal in time domain\nwith high speed. I will introduce a few ADC architectures and/or techniques that demonstrate promises\nin achieving high conversion rate but at a low area and/or power consumption\, including some silicon\nexamples developed in my research group.\nSpeaker(s): Mike Chen\,\nAgenda:\nNetworking: 4:00 pm – 5:00 pm (PT)\nPresentation: 5:00 pm – 6:00 pm (PT)\nRoom: 116\, Bldg: Bergin Hall\, 500 El Camino Real\, Santa Clara University\, Santa Clara\, California\, United States\, 95053
URL:https://svec.org/event/title-trend-and-opportunities-for-high-speed-gs-s-adcs/
LOCATION:Room: 116\, Bldg: Bergin Hall\, 500 El Camino Real\, Santa Clara University\, Santa Clara\, California\, United States\, 95053
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