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SUMMARY:The Role of Digital Twins in Semiconductor Manufacturing Control
DESCRIPTION:ABSTRACT\nDigital twin (DT) is a relatively new technology concept with potential to improve semiconductor wafer\nprocessing. Development of this technology has been evolutionary and a direct result of the confluence\nof advances in high-performance computing\, network communication\, optimization techniques\, sensing\ntechnologies and the use of vast array of sensors for process monitoring. Potential application of DT\ntechnology to semiconductor equipment includes predictive maintenance\, fault detection\, performance\nevaluation\, and chamber matching. Following a discussion of the DT concept\, this talk will focus on SC’s\nexperience with the most challenging aspect of DT technology – development of fast subsystem models\nthat may be subsequently integrated to create a digital twin of a system. In most cases\, these low-order\nmodels have been developed from high-order\, high-fidelity physical models whose simulations run too\nslow for DT application. SC has an extensive background and experience in using various model-order\nreduction techniques to develop such fast models of various semiconductor equipment such as RTP\,\nplasma etch\, CMP\, and bake lithography systems. SC has successfully used these models for closed-loop\nreal time process control\, virtual sensing\, and chamber matching. Additionally\, we describe a couple of\nour research projects on non-manufacturing applications that are relevant. In one\, a low-order model of\na complex system was developed by combining physics-based modeling with machine learning (deep\nneural network\, or DNN) so that the user would be warned when changes to the system warranted that\nthe DNN be retrained. In another project\, a complete DT of a large structural system was developed that\nis still in operation.\nSpeaker(s): Abbas\nAgenda:\n6:00 – 6:30 – Networking and light dinner (for in person attendees)\n6:30 – 7:30 – Talk and Q & A\n7:30 – 8:00 – Wrap up and Networking\nRoom: 3116\, Bldg: SCDI\, Santa Clara University\, 500 El Camino Real\, Santa Clara\, California\, United States\, 95053\, Virtual: https://events.vtools.ieee.org/m/475484
URL:https://svec.org/event/the-role-of-digital-twins-in-semiconductor-manufacturing-control/
LOCATION:Room: 3116\, Bldg: SCDI\, Santa Clara University\, 500 El Camino Real\, Santa Clara\, California\, United States\, 95053\, Virtual: https://events.vtools.ieee.org/m/475484
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