BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Silicon Valley Engineering Council - ECPv6.16.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Silicon Valley Engineering Council
X-ORIGINAL-URL:https://svec.org
X-WR-CALDESC:Events for Silicon Valley Engineering Council
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250501T174000
DTEND;TZID=America/Los_Angeles:20250501T192000
DTSTAMP:20260513T124326
CREATED:20250423T221837Z
LAST-MODIFIED:20250423T221837Z
UID:69006-1746121200-1746127200@svec.org
SUMMARY:Scaling Enterprise IoT
DESCRIPTION:Building Enterprise IoT to scale out to millions of devices worldwide is a challenging problem. Enterprise IoT has various use cases all of which require creative ways of scaling. Join Abhishek Bhattacharyya\, senior Technical Leader at Cisco to find out how the industry is adapting to some of the scaling challenges in terms of device ecosystem\, device lifetime\, and IoT infrastructure.\nSpeaker(s): \, Abhishek Bhattacharyya\nAgenda:\n5:40 – 6:00 PM\nArrival\, Networking & Pizza\n6:00 – 6:45 PM\nPresentation\n6:45 – 7:00 PM\nQ&A Session\n7:00 – 7:20 PM\nClosing Networking\nRoom: 1308\, Bldg: SCDI\, 500 El Camino Real\, Santa Clara \, California\, United States\, 95053
URL:https://svec.org/event/scaling-enterprise-iot/
LOCATION:Room: 1308\, Bldg: SCDI\, 500 El Camino Real\, Santa Clara \, California\, United States\, 95053
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250501T183000
DTEND;TZID=America/Los_Angeles:20250501T200000
DTSTAMP:20260513T124326
CREATED:20250326T093308Z
LAST-MODIFIED:20250326T093308Z
UID:67836-1746124200-1746129600@svec.org
SUMMARY:Got a Lot of Chip Designin’ to Do
DESCRIPTION:Chiplets are now the standard way to design chips at leading-edge nodes for applications such as AI and high-performance computing. Obvious challenges include the new stage of heterogeneous integration\, the new bus that connects the chiplets\, and the new advanced packages that hold it all together. No more afterthoughts; packaging\, test\, integration\, and manufacturing must all start right with the design. And design teams and foundry teams must work closely together to achieve the best result. Power\, thermal\, and other analyses must evaluate both individual chiplets and the system-as-a-whole (including the package). The foundry will play a larger role than ever before because it will generally provide a choice of packages and perform the integration\, and it will need fully tested (known good) dies to avoid wasting time and money on chips that fail inspection.\nSpeaker(s): Jawad Nasrullah\,\nRoom: 225\, Bldg: Heafey\, Santa Clara University\, Santa Clara\, California\, United States\, Virtual: https://events.vtools.ieee.org/m/477704
URL:https://svec.org/event/got-a-lot-of-chip-designin-to-do/
LOCATION:Room: 225\, Bldg: Heafey\, Santa Clara University\, Santa Clara\, California\, United States\, Virtual: https://events.vtools.ieee.org/m/477704
END:VEVENT
END:VCALENDAR