BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Silicon Valley Engineering Council - ECPv6.16.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://svec.org
X-WR-CALDESC:Events for Silicon Valley Engineering Council
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250627T113000
DTEND;TZID=America/Los_Angeles:20250627T130000
DTSTAMP:20260619T032618
CREATED:20250603T031809Z
LAST-MODIFIED:20250603T031809Z
UID:75917-1751023800-1751029200@svec.org
SUMMARY:Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits
DESCRIPTION:As Moore’s Law is slowing down and eventually approaching an end for conventional CMOS\, new platforms for producing circuit-level innovation are desired. At the same time\, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. This talk presents an overview of the 10-year research program\, which is a “vertical” innovative platform by “inserting” III-V layers into a conventional Si-CMOS foundry process. The talk also presents a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-integrated technology.\nWhen: Friday\, June 27th\, 2025 – 11:30AM to 1PM (PDT)\n11:30AM – 12PM: Networking / Pizza\n12PM-12:45PM: Lecture\n12:45PM-12:55PM: Q&A\n1PM Adjourn\nBio:\nDr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983\, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990\, respectively. He has been with the School of Electrical and Electronic Engineering\, Nanyang Technological University (NTU)\, Singapore from 1992 to 2024. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His research at NTU mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk\, SOI\, double-gate\, nanowire CMOS\, as well as III-V HEMTs. He has given more than 150 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. Dr. Zhou was the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference (2002–2018). He was an editor for the IEEE Electron Device Letters (2007–2016)\, a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices\, and a member of the Modeling & Simulation subcommittee for IEDM (2016\, 2017). He was an Elected Member-at-Large of EDS Board of Governors (2004–2009; 2011–2016) and served as Vice-President for Regions/Chapters (2013–2015). He has been an EDS Distinguished Lecturer since 2000. He is a Life Senior Member of the IEEE and currently serves as chair for the RS/EPS/EDS Singapore Joint Chapter.\nSunnyvale\, California\, United States\, Virtual: https://events.vtools.ieee.org/m/487617
URL:https://svec.org/event/monolithic-co-integration-of-iii-v-materials-into-foundry-si-cmos-in-a-single-chip-for-novel-integrated-circuits/
LOCATION:Sunnyvale\, California\, United States\, Virtual: https://events.vtools.ieee.org/m/487617
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20250627T183000
DTEND;TZID=America/Los_Angeles:20250627T200000
DTSTAMP:20260619T032618
CREATED:20250417T020327Z
LAST-MODIFIED:20250417T020327Z
UID:68680-1751049000-1751054400@svec.org
SUMMARY:Artificial Intelligence-Assisted Design and Fault Diagnosis of Electric Motors for Green Transportation
DESCRIPTION:A talk by Prof. Min-Fu Hsieh of National Cheng Kung University (NCKU)\, Tainan Taiwan\, exploring the integration of AI in diagnosing motor faults and advancing motor design\, highlighting how AI can significantly enhance the reliability and performance of electric motors in green transportation. It will delve into the use of machine learning and deep learning models to predict and prevent motor failures (e.g.\, inter-turn short-circuits\, demagnetization\, and bearing faults)\, which is essential for ensuring safety and reliability in transportation and industry. Furthermore\, the talk will highlight AI-driven innovations in motor design\, such as noise-reduction\, offering insights into how AI can revolutionize traditional motor systems and contribute to ongoing improvements in predictive maintenance and design practices.\nAgenda:\n6:30 – 7:00	Socializing and Networking at Quadrant\n6:55	Zoom session will be online with Waiting Room\n7:00 – 7:45	Lecture begins\, online and in person\n7:45 – 8:00	Questions and Answers\n1120 Ringwood Ct\, San Jose\, California\, United States\, 95131\, Virtual: https://events.vtools.ieee.org/m/481023
URL:https://svec.org/event/artificial-intelligence-assisted-design-and-fault-diagnosis-of-electric-motors-for-green-transportation/
LOCATION:1120 Ringwood Ct\, San Jose\, California\, United States\, 95131\, Virtual: https://events.vtools.ieee.org/m/481023
END:VEVENT
END:VCALENDAR