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DTSTART;TZID=America/Los_Angeles:20251113T113000
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UID:77174-1763033400-1763039700@svec.org
SUMMARY:Rethinking Chip Design to deliver Faster\, Smarter\, More Compact Solutions
DESCRIPTION:Rethinking Chip Design to deliver Faster\, Smarter\, More Compact Solutions\n[]\nAbstract:\nCDimension is rethinking chip design from the ground up\, delivering solutions that are faster\, smarter\, and more compact.\nWe’re moving beyond the limitations of traditional technology.\nOur foundational innovations in advanced materials and semiconductor integration unlock unprecedented gains in performance\, efficiency\, and scalability – ranging from 10x to 1\,000x times greater than current approaches.\nOur first milestone: the commercial release of ultra-thin 2D semiconductor materials — a foundational step toward our vision of vertically integrated systems that unify compute\, memory\, and power.\n[]\nSpeaker:\nDr. Jiadi Zhu\nCEO\nCDimension\nJiadi Zhu is the CEO and founder of CDimension\, a company rethinking chip design to deliver faster\, smarter\, more compact solutions for the most demanding and complex computing workloads. His vision is to redefine how chips are designed\, not just for higher performance\, but for fundamentally better structure and efficiency.\nJiadi’s technical foundation spans over a decade of work at the frontier of 2D materials\, monolithic 3D integration\, and device scaling. He earned his Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology and has been recognized across both academia and industry for his originality in device design\, novel semiconductor materials\, and integration.\nHis research–from MIT to the lab bench of CDimension–has focused on how to break architectural bottlenecks through physics-aware\, layout-driven design. Jiadi’s research has been widely cited in the field and published and presented in top-tier journals and conferences\, including Nature Nanotechnology and IEEE’s International Electron Devices Meeting.\nJiadi’s transition from research into startup leadership has drawn attention from leaders in semiconductors\, high-performance computing\, and next-generation AI hardware. Today\, under Jiadi’s leadership\, CDimension is overcoming the limitations of traditional chip architectures and delivering significantly better performance\, efficiency\, and scalability across modern computing environments.\nAGENDA:\nThursday November 13\, 2025\n11:30 AM: Networking\, Pizza & Drinks\nNoon — 1 pm: Seminar\nPlease register on Eventbrite before 9:30 AM on Thursday November 13\, 2025\n$4 IEEE members $6 non IEEE members\n(discounts for unemployed and students )\nSee examplesAdd\nCo-sponsored by: 636940-Santa Clara Valley Section Chapter\,EMB18\nBldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road\, EAG Labs\, 810 Kifer Road\, Sunnyvale\, California\, California\, United States\, 95051
URL:https://svec.org/event/rethinking-chip-design-to-deliver-faster-smarter-more-compact-solutions/
LOCATION:Bldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road\, EAG Labs\, 810 Kifer Road\, Sunnyvale\, California\, California\, United States\, 95051
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DTSTART;TZID=America/Los_Angeles:20251113T120000
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DTSTAMP:20260515T045643
CREATED:20250829T103326Z
LAST-MODIFIED:20250829T103326Z
UID:77010-1763035200-1763038800@svec.org
SUMMARY:AI-Enhanced Multimodal Approaches for Electronics Metrology and Failure Analysis
DESCRIPTION:The rapid growth of 3D advanced packaging introduces new challenges in inspection and failure analysis\, where complex structures such as microbumps\, redistribution layers (RDLs)\, and through-silicon vias (TSVs) demand reliable non-destructive testing (NDT). Conventional approaches\, including Scanning Acoustic Microscopy (SAM) and X-ray imaging\, are limited by noise\, resolution\, and defect visibility\, creating barriers for reproducible and scalable analysis. To address these challenges\, our work advances an AI-powered multimodal inspection framework that couples physics-informed machine learning with structured data infrastructure. A Physics-Informed Neural Network (PINN) approach enhances SAM imaging by embedding acoustic wave physics into reconstructions\, producing higher-fidelity images validated through structural similarity and physical accuracy metrics. Complementing this\, multimodal data fusion across SAM\, X-ray laminography\, optical microscopy\, and CT establishes richer defect detection and cross-validation. Central to this effort is the creation of multimodality benchmark datasets built on standardized acquisition protocols\, structured metadata schemas\, and annotation pipelines. These datasets provide not only a foundation for AI model training but also enable reproducibility\, traceability\, and interoperability across future programs.\nSpeaker(s): Navid Asadi\,\nVirtual: https://events.vtools.ieee.org/m/498529
URL:https://svec.org/event/ai-enhanced-multimodal-approaches-for-electronics-metrology-and-failure-analysis/
LOCATION:Virtual: https://events.vtools.ieee.org/m/498529
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