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UID:77182-1765443600-1765447200@svec.org
SUMMARY:AI for Thermal Management of Electronic Systems: A Pathway to Digital Twins
DESCRIPTION:[]The rapid rise in power density and complexity of electronic systems has made thermal management a critical challenge for ensuring reliability\, performance\, and sustainability. Artificial Intelligence (AI) offers transformative opportunities to address this challenge by enabling data-driven modeling\, optimization\, and predictive control of cooling systems. By integrating AI with experimental and physics-based approaches\, adaptive models can be developed to capture transient thermal behaviors\, and optimize system-level energy efficiency. This forms the foundation for digital twins\, virtual replicas that continuously interact with their physical counterparts to provide system specific real-time monitoring\, and data driven decision support. In this talk\, I will present recent and ongoing research activities at ES2 Binghamton on AI-enabled thermal management design\, with emphasis on cooling solutions for high-power chips in data centers. I will further highlight how these developments serve as a pathway towards creating digital twins\, dynamic virtual replicas that integrate real-time data\, physics\, and AI to enable system-level monitoring\, prediction\, and optimization. Together\, these advancements pave the way for reliable\, energy-efficient\, and sustainable electronic systems.\nSpeaker(s): Srikanth Rangarajan\,\nVirtual: https://events.vtools.ieee.org/m/504510
URL:https://svec.org/event/ai-for-thermal-management-of-electronic-systems-a-pathway-to-digital-twins/
LOCATION:Virtual: https://events.vtools.ieee.org/m/504510
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DTSTART;TZID=America/Los_Angeles:20251211T120000
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DTSTAMP:20260428T044100
CREATED:20250924T110400Z
LAST-MODIFIED:20250924T110400Z
UID:77148-1765454400-1765458000@svec.org
SUMMARY:Digital Lithography: Addressing Scaling Challenges in Advanced Packaging
DESCRIPTION:[]\nRequirements on the high-performance compute (HPC) systems from AI workloads necessitates transition to larger package sizes with 2.5D to 3.5D integration and density scaling at every level in the stack. Several competing packaging architectures are emerging to solve the compute and power efficiency challenge presented by AI workloads. Each presents unique lithography challenges such as >100×100 field size\, large chip placement deviations\, fine lines and tight overlay warped substrates. The conventional lithography tools are incapable of meeting all the requirements to achieve scaling.\nThe talk will preview Applied Materials’ Digital Lithography Technology (DLT) which enables highest resolution at production throughputs while ensuring CD uniformity and overlay accuracy across the entire panel.\nSpeaker(s): Niranjan Khasgiwale\,\nVirtual: https://events.vtools.ieee.org/m/502777
URL:https://svec.org/event/digital-lithography-addressing-scaling-challenges-in-advanced-packaging/
LOCATION:Virtual: https://events.vtools.ieee.org/m/502777
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