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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260729T173000
DTEND;TZID=America/Los_Angeles:20260729T193000
DTSTAMP:20260702T173324Z
CREATED:20260702T173324Z
LAST-MODIFIED:20260702T173324Z
UID:78617-1785346200-1785353400@svec.org
SUMMARY:Engaging Video Analytics and Generative AI
DESCRIPTION:In this talk\, Dr. Jianquan Liu presents an industry perspective on the convergence of video analytics and generative AI. The talk begins with an overview of video analytics\, covering advancements in action recognition\, object tracking\, human-object interactions\, scene recognition\, and behavioral pattern analysis. These technologies enable efficient extraction\, retrieval\, visualization\, and summarization of video content. The presentation then explores the impact of generative AI\, particularly large language models (LLMs)\, on video understanding. It discusses how LLMs enhance object recognition\, semantic segmentation\, action recognition\, captioning\, visual question answering\, and storytelling. Dr. Liu provides industry case studies to illustrate these applications while also addressing limitations and challenges. The talk introduces NEC's narrative summarization framework\, designed to tackle key challenges in video analytics. It concludes with a demonstration of "Video with LLM" technology\, showcasing its practical application in automating traffic accident investigation reports. This presentation offers valuable insights into the current state and future potential of AI-driven video intelligence\, bridging the gap between technical innovation and practical application for both industry professionals and general audiences.\nCo-sponsored by: Oakland-East Bay Section Chapter\nSpeaker(s): Jianquan Liu \,\nAgenda:\n– 5:30 PM – 6:00 PM: Networking\n– 6:00 PM – 7:30 PM: Presentation\, Q&A\nSobrato Campus for Discovery and Innovation (SCDI) Room 1302\, 500 El Camino Real\, Santa Clara\, California\, United States\, 95053
URL:https://svec.org/event/engaging-video-analytics-and-generative-ai/
LOCATION:Sobrato Campus for Discovery and Innovation (SCDI) Room 1302\, 500 El Camino Real\, Santa Clara\, California\, United States\, 95053
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260729T180000
DTEND;TZID=America/Los_Angeles:20260729T193000
DTSTAMP:20260701T173305Z
CREATED:20260701T173305Z
LAST-MODIFIED:20260701T173305Z
UID:78592-1785348000-1785353400@svec.org
SUMMARY:IEEE Oakland-East Bay Communications Society Distinguished Lecturer Series
DESCRIPTION:The IEEE Oakland-East Bay Communications Society Chapter is pleased to host an IEEE Communications Society Distinguished Lecturer presentation by Dr. Wei Gao\, Principal Engineer at Broadcom.\nPresentation Title\nMeta-Learning-Assisted Predistortion for Power Amplifier Linearization in Wireless Communication Systems\nAbstract\nModern wireless communication systems require highly efficient RF power amplifiers while maintaining excellent signal linearity. This presentation introduces recent advances in AI-assisted digital predistortion techniques\, focusing on meta-learning-based approaches that improve power amplifier linearization for IEEE 802.11 Wi-Fi systems. The talk discusses practical implementation challenges\, optimization techniques\, and industrial applications developed through years of experience at Broadcom.\nSpeaker\nDr. Wei Gao\nIEEE Communications Society Distinguished Lecturer (2025–2026)\nPrincipal Engineer\, Broadcom\nEveryone is welcome\, including IEEE members\, students\, researchers\, and industry professionals.\nSpeaker(s): Wei Gao\nAgenda:\n• Welcome and Chapter Update\n• Distinguished Lecturer Presentation\n• Live Questions and Discussion\nVirtual: https://events.vtools.ieee.org/m/565708
URL:https://svec.org/event/ieee-oakland-east-bay-communications-society-distinguished-lecturer-series/
LOCATION:Virtual: https://events.vtools.ieee.org/m/565708
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260729T180000
DTEND;TZID=America/Los_Angeles:20260729T193000
DTSTAMP:20260701T173305Z
CREATED:20260701T173305Z
LAST-MODIFIED:20260701T173305Z
UID:78593-1785348000-1785353400@svec.org
SUMMARY:IEEE Oakland-East Bay Communications Society Distinguished Lecturer Series
DESCRIPTION:The IEEE Oakland-East Bay Communications Society Chapter is pleased to host an IEEE Communications Society Distinguished Lecturer presentation by Dr. Wei Gao\, Principal Engineer at Broadcom.\nPresentation Title\nMeta-Learning-Assisted Predistortion for Power Amplifier Linearization in Wireless Communication Systems\nAbstract\nModern wireless communication systems require highly efficient RF power amplifiers while maintaining excellent signal linearity. This presentation introduces recent advances in AI-assisted digital predistortion techniques\, focusing on meta-learning-based approaches that improve power amplifier linearization for IEEE 802.11 Wi-Fi systems. The talk discusses practical implementation challenges\, optimization techniques\, and industrial applications developed through years of experience at Broadcom.\nSpeaker\nDr. Wei Gao\nIEEE Communications Society Distinguished Lecturer (2025–2026)\nPrincipal Engineer\, Broadcom\nEveryone is welcome\, including IEEE members\, students\, researchers\, and industry professionals.\nSpeaker(s): Wei Gao\nAgenda:\n• Welcome and Chapter Update\n• Distinguished Lecturer Presentation\n• Live Questions and Discussion\nVirtual: https://events.vtools.ieee.org/m/565708
URL:https://svec.org/event/ieee-oakland-east-bay-communications-society-distinguished-lecturer-series-2/
LOCATION:Virtual: https://events.vtools.ieee.org/m/565708
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260730T180000
DTEND;TZID=America/Los_Angeles:20260730T210000
DTSTAMP:20260630T171854Z
CREATED:20260630T171854Z
LAST-MODIFIED:20260630T171854Z
UID:78575-1785434400-1785445200@svec.org
SUMMARY:Video Coding Standards in the Age of AI
DESCRIPTION:The IEEE Signal Processing Society Industry Board and Santa Clara Valley Chapter are pleased to announce an upcoming event on Video Coding Standards in the Age of AI which will be held on July 30\, 2026 in Palo Alto\, CA.\nAs AI continues to evolve\, it is playing an increasingly important role in next-generation signal processing and multimedia technologies. At the same time\, major international and open-source standardization organizations are actively exploring how AI can be integrated into future standards. This event will bring together experts from industry and the standards community to discuss the latest advances in AI for video coding\, current standardization efforts\, and future research directions.\nSpeakers\nThis event features distinguished speakers from industry and standardization community:\n– Arianne Hinds (INCITS L3 Chair)\n– Debargha Mukherjee (Google\, Principal Engineer / Director)\n– Alican Nalci (Meta\, Research Scientist)\n– Leo Zhao (Tencent\, Principal Research Scientist)\nWhether you are a researcher\, engineer\, student\, or practitioner interested in AI and video compression\, we warmly welcome you to join us for an evening of technical discussions and networking with leaders from academia and industry.\nCo-sponsored by: IEEE Signal Processing Society Industry Board\nSpeaker(s): Arianne Hinds \, Debargha Mukherjee \, Alican Nalci\, Leo Zhao\nAgenda:\nAgenda\nThe evening event will feature invited talks and an interactive panel discussion on the intersection of AI and video coding\, covering the latest research advances\, standardization efforts\, and future trends.\n– 6:00 PM – 6:30 PM: Networking\n– 6:30 PM – 8:30 PM: Invited Talks\n– 8:30 PM – 9:00 PM: Panel Discussion\nRoom: Tai Meeting Room\, Bldg: Tencent Office\, Tencent Office\, 2747 Park Blvd\, Palo Alto\, California\, United States\, 94306
URL:https://svec.org/event/video-coding-standards-in-the-age-of-ai/
LOCATION:Room: Tai Meeting Room\, Bldg: Tencent Office\, Tencent Office\, 2747 Park Blvd\, Palo Alto\, California\, United States\, 94306
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260806T160000
DTEND;TZID=America/Los_Angeles:20260806T170000
DTSTAMP:20260626T164822Z
CREATED:20260626T164822Z
LAST-MODIFIED:20260626T164822Z
UID:78563-1786032000-1786035600@svec.org
SUMMARY:Dual Seed Semi-Additive and Damascene Processes: Enabling Fine-Pitch Interconnects for Advanced Packaging
DESCRIPTION:[]\nAs AI\, high-performance computing\, and heterogeneous integration continue to scale\, advanced packaging is facing growing interconnect challenges across redistribution layers\, IC substrates\, HDI boards\, silicon vias\, and emerging glass-core platforms. Higher bandwidth and larger package form factors require finer wiring\, smaller vias\, higher fan-out density\, and more reliable vertical interconnects. In this context\, copper seed formation and via metallization are becoming increasingly important bottlenecks for next-generation package and substrate scaling.\nConventional copper deposition technologies\, including physical vapor deposition\, electroless plating\, and electroplating\, each play essential roles in today’s manufacturing flows. However\, as via structures become smaller\, deeper\, rougher\, or higher in aspect ratio\, limitations such as step coverage\, liquid circulation\, process uniformity\, and seed-layer continuity become more difficult to manage. These challenges are especially relevant across multiple interconnect layers\, including motherboard HDI PCBs\, IC substrates\, RDL\, memory and interposer silicon vias\, and Si BEOL metal\, etc.\nThis presentation will introduce Nano Copper Deposition as a solution family for AI-era interconnect scaling. The talk will cover DeepVia™ HDI for high-aspect-ratio via metallization in motherboard HDI PCBs\, DS-SAP™ for resolving the trade-off between thin surface seed layers and robust via coverage in IC substrates\, and other applications such as Dual Seed Damascene for fine and high-aspect-ratio damascene structures in BEOL and RDL applications\, and DeepVia™ Silicon for memory and interposer silicon vias. The discussion will highlight how these approaches can support higher I/O density\, improved escape routing\, reduced layer-count dependency\, and broader process flexibility for next-generation advanced packaging.\nSpeaker(s): Shinya Shimizu\,\nVirtual: https://events.vtools.ieee.org/m/565310
URL:https://svec.org/event/dual-seed-semi-additive-and-damascene-processes-enabling-fine-pitch-interconnects-for-advanced-packaging/
LOCATION:Virtual: https://events.vtools.ieee.org/m/565310
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260819T190000
DTEND;TZID=-07:00:20260819T210000
DTSTAMP:20260506T213309Z
CREATED:20260506T213309Z
LAST-MODIFIED:20260506T213309Z
UID:78402-1787166000-1787173200@svec.org
SUMMARY:Modern Test Automation & Quality Engineering in Agile Systems
DESCRIPTION:LOCATION ADDRESS (Hybrid\, in person or by zoom\, you choose)\nValley Research Park\n319 North Bernardo Avenue\nMountain View\, CA CA 93043\nDon’t use the front door. When facing the front door\, turn right along the front of the building. Turn left around the building corner. The 2nd door should be open and have a banner and event registration. \nIf you want to join remotely\, you can submit questions via Zoom Q&A. The zoom link:\n[https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1](https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1)\nJoin via YouTube:\n[https://youtube.com/live/cu5TDl8N2Mk](https://youtube.com/live/cu5TDl8N2Mk) \nAGENDA\n6:30 Door opens\, food and networking (we invite honor system contributions)\n**7:00** SFBayACM upcoming events\, introduce the speaker\n7:15 speaker presentation starts\n8:15 – 8:30 finish\, depending on Q&A \nJoin SF Bay ACM Chapter for an insightful discussion on: \n**Talk Description**: \nAs software delivery accelerates\, traditional testing approaches struggle to keep pace with Agile and DevOps environments. Modern systems demand more than automated test cases—they require a shift toward quality engineering practices that embed reliability\, scalability\, and continuous feedback into every stage of development. \nThis talk explores how test automation has evolved from a validation activity into a core engineering discipline. We will examine how to design resilient automation frameworks\, integrate testing seamlessly into CI/CD pipelines\, and build quality signals that provide real-time insight into system health.\nThrough practical examples\, the session will highlight strategies for moving beyond UI-driven automation toward API\, integration\, and workflow-level validation. It will also cover key aspects such as test data management\, environment stability\, performance considerations\, and accessibility as part of continuous quality. \nAttendees will gain a clear understanding of how to align automation with Agile delivery\, reduce flaky tests\, and create scalable\, maintainable solutions that support rapid releases without compromising quality.\nThis session is designed for engineers and quality professionals who want to modernize their automation approach and build systems that are reliable by design\, not just tested after the fact. \n**Speaker Bio**:\nShri Lakshmi Rajagopal\, a Senior Quality Engineering Leader and Test Automation Architect. She has over 14 years of experience in software quality engineering\, automation architecture\, and engineering leadership. Her work focuses on designing maintainable automation frameworks\, enabling Agile quality practices\, and mentoring teams to adopt modern testing strategies. She is passionate about sharing practical insights that help teams build reliable and scalable software systems. \nLinkedIn:[https://www.linkedin.com/in/shri-lakshmi-rajagopal-a5012428](https://www.linkedin.com/in/shri-lakshmi-rajagopal-a5012428) \n— \nValley Research Park is a coworking research campus of 104\,000 square feet hosting 60+ life science and technology companies. VRP has over 100 dry labs\, wet labs\, and high power labs sized from 125-15\,000 square feet. VRP manages all of the traditional office elements: break rooms\, conference rooms\, outdoor dining spaces\, and recreational spaces. \nAs a plug-and-play lab space\, once companies have secured their next milestone and are ready to expand\, VRP has 100+ labs ready to expand into.\nhttps://www.valleyresearchpark.com/
URL:https://svec.org/event/modern-test-automation-quality-engineering-in-agile-systems/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/05/1024x576-NfPn4j.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260908T190000
DTEND;TZID=America/Los_Angeles:20260908T210000
DTSTAMP:20260625T164807Z
CREATED:20260625T164807Z
LAST-MODIFIED:20260625T164807Z
UID:78559-1788894000-1788901200@svec.org
SUMMARY:Rewired for AI: An Introduction to UltraEthernet
DESCRIPTION:As AI and HPC workloads scale exponentially\, traditional network fabrics are hitting a critical bottleneck. Legacy Ethernet simply wasn’t built for the ultra-low latency and zero-loss tolerances demanded by next-generation clusters. This talk will provide an engineering-first primer on UltraEthernet—the industry’s collaborative answer to modern data center scaling.\nRip Sohan will dissect the architectural gaps of legacy networks\, analyze the new data plane building blocks\, and unpack the specification’s advanced congestion control and reliability mechanisms. He will also explore how UltraEthernet integrates with existing RDMA ecosystems. Attendees will leave with a definitive mental model of the fabric designed to power the future of compute.\nSpeaker(s): Rip Sohan\,\n925 Thompson Place\, Sunnyvale\, California\, United States\, 94085\, Virtual: https://events.vtools.ieee.org/m/565084
URL:https://svec.org/event/rewired-for-ai-an-introduction-to-ultraethernet/
LOCATION:925 Thompson Place\, Sunnyvale\, California\, United States\, 94085\, Virtual: https://events.vtools.ieee.org/m/565084
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260910T183000
DTEND;TZID=America/Los_Angeles:20260910T200000
DTSTAMP:20260713T181808Z
CREATED:20260713T181808Z
LAST-MODIFIED:20260713T181808Z
UID:78651-1789065000-1789070400@svec.org
SUMMARY:Permanent Magnets\, A Material in Flux
DESCRIPTION:Dr. Stan Trout of Spontaneous Materials will discuss how changing tariffs\, domestic sourcing requirements\, and global market forces are reshaping the permanent magnet industry and what these trends mean for its future. With nearly 50 years of experience in permanent magnets\, magnetic materials\, and rare-earth technologies\, Dr. Trout is widely recognized as a leading authority in the field.\nFor more information\, see (https://scvmag.org/event/20260910/)\nSpeaker(s): Dr. Stan Trout\nQuadrant Corp\, 1120 Ringwood Ct.\, San Jose\, California\, United States\, 95131\, Virtual: https://events.vtools.ieee.org/m/567538
URL:https://svec.org/event/permanent-magnets-a-material-in-flux/
LOCATION:Quadrant Corp\, 1120 Ringwood Ct.\, San Jose\, California\, United States\, 95131\, Virtual: https://events.vtools.ieee.org/m/567538
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260916T190000
DTEND;TZID=-07:00:20260916T210000
DTSTAMP:20260506T213309Z
CREATED:20260506T213309Z
LAST-MODIFIED:20260506T213309Z
UID:78404-1789585200-1789592400@svec.org
SUMMARY:Beyond the Buzzwords: The Real Engineering Challenges of Augmented Reality
DESCRIPTION:LOCATION ADDRESS (Hybrid\, in person or by zoom\, you choose)\nValley Research Park\n319 North Bernardo Avenue\nMountain View\, CA CA 93043\nDon’t use the front door. When facing the front door\, turn right along the front of the building. Turn left around the building corner. The 2nd door should be open and have a banner and event registration. \nIf you want to join remotely\, you can submit questions via Zoom Q&A. The zoom link:\n[https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1](https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1)\nJoin via YouTube:\n[https://youtube.com/live/cu5TDl8N2Mk](https://youtube.com/live/cu5TDl8N2Mk) \nAGENDA\n6:30 Door opens\, food and networking (we invite honor system contributions)\n**7:00** SFBayACM upcoming events\, introduce the speaker\n7:15 speaker presentation starts\n8:15 – 8:30 finish\, depending on Q&A \nJoin SF Bay ACM Chapter for an insightful discussion on: \n**Talk Description**:\nTalk description: Augmented Reality is often talked about in terms of its potential\, but what does it actually take to build it? This talk offers a candid\, high-level look at the engineering challenges that make AR glasses hard\, from power and thermals to silicon design\, and what it means to optimize at every layer of the stack to bring a product to life. \nReading material/blogs:\n[https://www.meta.com/blog/orion-ar-glasses-augmented-reality/](https://www.meta.com/blog/orion-ar-glasses-augmented-reality/)\n[https://www.meta.com/blog/boz-to-the-future-episode-22-wearables-orion-ray-ban-meta-alex-himel/](https://www.meta.com/blog/boz-to-the-future-episode-22-wearables-orion-ray-ban-meta-alex-himel/)\n[https://www.meta.com/blog/orion-compute-puck-reality-labs-next-computing-platform/](https://www.meta.com/blog/orion-compute-puck-reality-labs-next-computing-platform/)\n[https://www.meta.com/blog/orion-custom-silicon-chips-ip-blocks-accelerators-ar-algorithms-energy-efficiency-reality-labs/](https://www.meta.com/blog/orion-custom-silicon-chips-ip-blocks-accelerators-ar-algorithms-energy-efficiency-reality-labs/) \n**Speaker Bio**:\n**Shanmathi Natarajan is a Silicon Power Architect with experience at Meta Reality Labs\, where she led end-to-end power architecture for next-generation AR glasses. Her work spanned the full silicon lifecycle\, from early-stage SoC power modeling and architectural exploration to post-silicon validation and real-world correlation\, with a focus on turning high-level design intent into measurable efficiency gains on final silicon.**\n**Her work includes driving significant use-case power reductions on wearable SoCs\, directly enabling better battery life and user experience on AR devices. Her expertise spans low-power design methodologies\, hardware-software co-design\, DVFS and power state architecture\, and cross-layer optimization across compute\, memory\, and interconnect subsystems.**\n**Her research interests lie at the hardware-software boundary\, where low-level architectural decisions in AR glasses\, GPU architectures\, and energy-constrained systems translate directly into product-level impact.** \nhttps://www.linkedin.com/in/shanmathi-natarajan \n— \nValley Research Park is a coworking research campus of 104\,000 square feet hosting 60+ life science and technology companies. VRP has over 100 dry labs\, wet labs\, and high power labs sized from 125-15\,000 square feet. VRP manages all of the traditional office elements: break rooms\, conference rooms\, outdoor dining spaces\, and recreational spaces. \nAs a plug-and-play lab space\, once companies have secured their next milestone and are ready to expand\, VRP has 100+ labs ready to expand into.\nhttps://www.valleyresearchpark.com/
URL:https://svec.org/event/beyond-the-buzzwords-the-real-engineering-challenges-of-augmented-reality/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/05/1024x576-s1XBmH.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260924T113000
DTEND;TZID=America/Los_Angeles:20260924T130000
DTSTAMP:20260711T180307Z
CREATED:20260711T180307Z
LAST-MODIFIED:20260711T180307Z
UID:78642-1790249400-1790254800@svec.org
SUMMARY:Glass-Core Packaging and Its Reliability
DESCRIPTION:In the past few years\, because of high-performance computing (HPC) driven by artificial intelligence (AI) and data centers in this AI era\, packaging using glass-core substrates has been attracting lots of traction. For example\, among others\, Intel’s one-trillion-transistors application processor with glass-core substrate is to be shipped by the end of 2030 (announced September 2023) and TSMC’s chip-on-panel-on-substrate (CoPoS) with glass-core interposer is to be shipped in Q1 of 2029 (announced April 2025). In this lecture\, a brief fundamental of through-glass via (TGV) and redistribution-layers (RDLs) of glass packaging will be presented. The advantages and disadvantages of glass\, silicon\, and organic will be discussed. Panel-level packaging vs. wafer-level packaging and the panel size will also be provided. Finally\, the effects of coefficient of thermal expansion (CTE) of glass-core substrate on the solder joint reliability on printed circuit board (PCB) will be presented. Some recommendations will be provided.\nSpeaker(s): John Lau\,\nSEMI World Headquarters\, 673 South Milpitas Blvd\, Milpitas\, California\, United States\, 95050
URL:https://svec.org/event/glass-core-packaging-and-its-reliability/
LOCATION:SEMI World Headquarters\, 673 South Milpitas Blvd\, Milpitas\, California\, United States\, 95050
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260928T190000
DTEND;TZID=-07:00:20260928T210000
DTSTAMP:20260602T223307Z
CREATED:20260602T223307Z
LAST-MODIFIED:20260602T223307Z
UID:78460-1790622000-1790629200@svec.org
SUMMARY:Practical Lessons from Building AI Infrastructure for Billion User Products
DESCRIPTION:Practical Lessons from Building AI Infrastructure for Billion-User Products with ML Systems \nLOCATION ADDRESS (Hybrid\, in person or by zoom\, you choose)\nValley Research Park\n319 North Bernardo Avenue\nMountain View\, CA CA 93043\nIf you want to join remotely\, you can submit questions via Zoom Q&A. The zoom link:\n[https://acm-org.zoom.us/j/](https://acm-org.zoom.us/j/99320216248?pwd=hmIZXJbNiS0F4hrJerx0ffnI8rbYOr.1)\nJoin via YouTube:\nhttps://youtube.com/live/sJ38lsfLfeU \nAGENDA\n6:30 Door opens\, SFBAY ACM 68 anniversary Cake and networking (we invite honor system contributions)\n**7:00** Upcoming events\, introduction of the speaker\n7:15 Speaker presentation\n8:15- 8:30 finish\, depending on Q&A \nJoin SF Bay ACM Chapter for an insightful discussion on: \nAbstract\nThis talk covers what it takes to move ML/AI systems from promising prototypes to production systems that are reliable\, observable\, scalable\, and maintainable. I will discuss common architecture patterns\, rollout strategies\, evaluation and monitoring loops\, operational failure modes\, and engineering tradeoffs that show up at large scale. The talk is intended for experienced computing professionals and can be adjusted to a 45-60 minute format with Q&A. \nSpeaker bio:\nSilu Panda is a Sr. Software Engineer at Linkedin.com. He has 6 years of experience building ML infrastructure used by billions of users\, including 4 years at LinkedIn. He holds a bachelors degree in computer science from IIT Bombay. His focus areas are ML systems\, scalable infrastructure\, software engineering\, and practical AI product execution.. \nhttps://www.linkedin.com/in/silupanda/ \n— \nValley Research Park is a coworking research campus of 104\,000 square feet hosting 30+ life science and technology companies. VRP has over 100 dry labs\, wet labs\, and high power labs sized from 125-15\,000 square feet. VRP manages all of the traditional office elements: break rooms\, conference rooms\, outdoor dining spaces\, and recreational spaces. \nAs a plug-and-play lab space\, once companies have secured their next milestone and are ready to expand\, VRP has 100+ labs ready to expand into.\nhttps://www.valleyresearchpark.com/
URL:https://svec.org/event/practical-lessons-from-building-ai-infrastructure-for-billion-user-products/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/06/1024x576-mQJE6V.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20261015T070000
DTEND;TZID=America/Los_Angeles:20261015T170000
DTSTAMP:20260605T160500Z
CREATED:20260605T160500Z
LAST-MODIFIED:20260605T160500Z
UID:78491-1792047600-1792083600@svec.org
SUMMARY:Electrical Design Fundamentals Seminar
DESCRIPTION:This one-day Technical Seminar will cover the fundamentals of electrical design\, cable ampacity\, protective relaying\, and interconnections. The seminar will serve as a primer for engineers and a refresher for experienced engineers. During breaks and lunch there will be opportunities to network with your peers and meet with manufacturers. The registration cost includes continental breakfast\, lunch\, and refreshments.\nPlease join us in attending this one-day Technical Seminar which will include an impressive list of speakers from IEEE\, Eaton\, Electrical Reliability Services (a Vertiv Company)\, ETAP\, SEL\, and NEMA. Seminar topics will include:\n– Overview of IEEE 1547-2018\, Standard for Interconnection and Interoperability of distributed energy resources (DER) with Electric Power Systems\n– Electrical Design Fundamentals – Circuit Breaker Applications Understood\n– Medium Voltage Cable Installations\n– Cable Ampacity and Sizing Fundamentals Generator\n– Protective Relaying Fundamentals\n– NEMA Resources and the NEMA Standards Store\nPlan to attend this timely\, educational Seminar. Registration is now open!\nFor Group Registrations\, please list all attendee email addresses under Special Requests.\n***** Early-Bird registration closes on July 3\, don’t delay!*****\n(Registration is limited to 100 attendees and must be completed on vTools. No walk-in registrations.)\nSpeaker(s): Chase Sun\, Chris Lovin\, Steve Park\, Avelardo Morales \, Angel Morales\, Mike Stone\nAgenda:\n8:00AM-4:30PM (sign-in opens at 7:15AM)\nDoubleTree by Hilton Hotel Pleasanton at The Club\, 7050 Johnson Drive\, Pleasanton\, California\, United States\, 94588
URL:https://svec.org/event/electrical-design-fundamentals-seminar/
LOCATION:DoubleTree by Hilton Hotel Pleasanton at The Club\, 7050 Johnson Drive\, Pleasanton\, California\, United States\, 94588
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20261015T070000
DTEND;TZID=America/Los_Angeles:20261015T170000
DTSTAMP:20260605T160500Z
CREATED:20260605T160500Z
LAST-MODIFIED:20260605T160500Z
UID:78490-1792047600-1792083600@svec.org
SUMMARY:VENDOR TABLE for Electrical Design Fundamentals Seminar
DESCRIPTION:*****This vTools link is for purchase of Vendor Tables ONLY! No walk-in registrations.*****\n(Limit of 10 vendor tables so do not delay!)\nVendor table will be one 6-foot exhibit table. Vendor table includes one (1) attendee ticket. A power strip will be available upon request.\nFor more than one (1) attendee to support the table\, please register additional people using the regular attendee link: https://events.vtools.ieee.org/m/562108\nTape\, Tacks\, Nails may not be applied to walls\, ceilings\, or doors and are strictly prohibited.\nOutside food\, non-alcoholic and alcoholic beverage are not allowed.\nIEEE and the Hotel are not responsible for any loss or damage to property belonging to you.\nSign-in for attendees and continental breakfast will open at 7:15AM\, so please be completely set up by 7:15AM.\nVendors are encouraged (voluntary) to bring up to three (3) giveaways to be included in the overall raffle for attendees.\nThis one-day Technical Seminar will cover the fundamentals of electrical design\, cable ampacity\, protective relaying\, and interconnections. The seminar will serve as a primer for engineers and a refresher for experienced engineers. During breaks and lunch there will be opportunities to network with your peers and meet with manufacturers. The registration cost includes continental breakfast\, lunch\, and refreshments.\nPlease join us in attending this one-day Technical Seminar which will include an impressive list of speakers from IEEE\, Eaton\, Electrical Reliability Services (a Vertiv Company)\, ETAP\, SEL\, and NEMA. Seminar topics will include:\n– Overview of IEEE 1547-2018\, Standard for Interconnection and Interoperability of distributed energy resources (DER) with Electric Power Systems\n– Electrical Design Fundamentals – Circuit Breaker Applications Understood\n– Medium Voltage Cable Installations\n– Cable Ampacity and Sizing Fundamentals Generator\n– Protective Relaying Fundamentals\n– NEMA Resources and the NEMA Standards Store\nPlan to attend this timely\, educational Seminar. Registration is now open!\nSpeaker(s): Chase Sun\, Chris Lovin\, Steve Park\, Avelardo Morales \, Angel Morales\, Mike Stone\nAgenda:\n8:00AM-4:30PM (sign-in opens at 7:15AM)\n*****Vendors should be set up and ready by 7:15AM.*****\nDoubleTree by Hilton Hotel Pleasanton at The Club\, 7050 Johnson Drive\, Pleasanton\, California\, United States\, 94588
URL:https://svec.org/event/vendor-table-for-electrical-design-fundamentals-seminar/
LOCATION:DoubleTree by Hilton Hotel Pleasanton at The Club\, 7050 Johnson Drive\, Pleasanton\, California\, United States\, 94588
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20261021T190000
DTEND;TZID=-07:00:20261021T210000
DTSTAMP:20260610T223305Z
CREATED:20260610T223305Z
LAST-MODIFIED:20260610T223305Z
UID:78512-1792609200-1792616400@svec.org
SUMMARY:Agentic AI doesnt have an Intelligence problem\, it has a Governance problem !!
DESCRIPTION:LOCATION ADDRESS (Hybrid\, in person or by zoom\, you choose)\nValley Research Park\n319 North Bernardo Avenue\nMountain View\, CA CA 93043\nDon’t use the front door. When facing the front door\, turn right along the front of the building. Turn left around the building corner. The 2nd door should be open and have a banner and event registration. \nIf you want to join remotely\, you can submit questions via Zoom Q&A. The zoom link:\n[https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1](https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1)\nJoin via YouTube:\n[https://youtube.com/live/cu5TDl8N2Mk](https://youtube.com/live/cu5TDl8N2Mk) \nAGENDA\n6:30 Door opens\, food and networking (we invite honor system contributions)\n**7:00** SFBayACM upcoming events\, introduce the speaker\n7:15 speaker presentation starts\n8:15 – 8:30 finish\, depending on Q&A \nJoin SF Bay ACM Chapter for an insightful discussion on: \n**Talk Description**:\nAs enterprises race to deploy autonomous AI agents\, much of the industry conversation remains focused on model capabilities: reasoning\, planning\, tool use\, and autonomy. Yet the greatest barrier to successful adoption may not be intelligence at all. It is governance. Unlike traditional AI systems that primarily generate recommendations\, agentic systems execute actions across interconnected business processes\, data platforms\, and operational workflows. In such environments\, failures rarely originate from model limitations alone. They emerge from hidden dependencies\, inconsistent data\, unclear ownership\, inadequate observability\, and the absence of effective operational controls. \n**Speaker bio:**\nSayantan Ghosh is a Senior Engineering Manager at LinkedIn\, where he runs the feed data platform serving billion+ members on LinkedIn Feed. He has previously built data and AI platforms at Meta\, Uber\, and eBay. He is an IEEE Senior Member\, holds a granted U.S. patent (US 9\,870\,355 B2)\, and is an invited speaker at various international venues like Big Data Europe\, Big Data Canada\, DataCon LA. He is a manuscript reviewer in leading Q1 journals IEEE TNNLS\, ACM TKDD\, IEEE TCDS\, Elsevier Neural Networks\, etc. Sayantan has mentored and grown several tech professionals across his decade long career at the most cutting edge companies in Silicon valley.\nLinkedIn: [https://www.linkedin.com/in/sayantanghosh/](https://www.linkedin.com/in/sayantanghosh/) \n— \nValley Research Park is a coworking research campus of 104\,000 square feet hosting 60+ life science and technology companies. VRP has over 100 dry labs\, wet labs\, and high power labs sized from 125-15\,000 square feet. VRP manages all of the traditional office elements: break rooms\, conference rooms\, outdoor dining spaces\, and recreational spaces. \nAs a plug-and-play lab space\, once companies have secured their next milestone and are ready to expand\, VRP has 100+ labs ready to expand into.\nhttps://www.valleyresearchpark.com/
URL:https://svec.org/event/agentic-ai-doesnt-have-an-intelligence-problem-it-has-a-governance-problem/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/06/1024x576-Nh6iuX.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20261026T190000
DTEND;TZID=-07:00:20261026T210000
DTSTAMP:20260614T223303Z
CREATED:20260614T223303Z
LAST-MODIFIED:20260614T223303Z
UID:78525-1793041200-1793048400@svec.org
SUMMARY:From Silent Data Failures to Enforceable CI/CD Gates
DESCRIPTION:LOCATION ADDRESS (Hybrid\, in person or by zoom\, you choose)\nValley Research Park\n319 North Bernardo Avenue\nMountain View\, CA 94043\nDon’t use the front door. When facing the front door\, turn right along the front of the building. Turn left around the building corner. The 2nd door should be open and have a banner and event registration. \nIf you want to join remotely\, you can submit questions via Zoom Q&A. The zoom link:\n[https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1](https://acm-org.zoom.us/j/95226212956?pwd=HnAedzSDGcYAYsCzTuavIvMYMFtILa.1)\nJoin via YouTube:\n[https://youtube.com/live/cu5TDl8N2Mk](https://youtube.com/live/cu5TDl8N2Mk) \nAGENDA\n6:30 Door opens\, food and networking (we invite honor system contributions)\n**7:00** SFBay ACM upcoming events\, introduce the speaker\n7:15 speaker presentation starts\n8:15 – 8:30 finish\, depending on Q&A \nJoin SF Bay ACM Chapter for an insightful discussion on: \n**Talk Description**:\nTraditional CI pipelines answer whether code builds and tests pass\, but data pipelines can deploy successfully while producing incorrect data. This session presents four enforceable gates organized by the defects they catch: transformation correctness\, cross-system integration\, contract compliance\, and production observability. It explains which gates should block merges\, which should block deployments\, and how production incidents should become lower-layer regression tests. Examples use Spark\, Kafka\, CDC\, and lakehouse failure modes. \nSpeaker Bio:\nKunal Jain\, Software Engineer 3 at Adobe. I build and operate large-scale data platforms and hold a Master of Software Engineering in Scalable Systems from Carnegie Mellon University. I previously spoke at STAREAST 2026.\nLinks: [https://kunal-jain.com](https://kunal-jain.com/) | [https://linkedin.com/in/kunalpjain](https://linkedin.com/in/kunalpjain) \n— \nValley Research Park is a coworking research campus of 104\,000 square feet hosting 60+ life science and technology companies. VRP has over 100 dry labs\, wet labs\, and high power labs sized from 125-15\,000 square feet. VRP manages all of the traditional office elements: break rooms\, conference rooms\, outdoor dining spaces\, and recreational spaces. \nAs a plug-and-play lab space\, once companies have secured their next milestone and are ready to expand\, VRP has 100+ labs ready to expand into.\nhttps://www.valleyresearchpark.com/
URL:https://svec.org/event/from-silent-data-failures-to-enforceable-ci-cd-gates/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/06/1024x576-htXfgi.jpg
END:VEVENT
END:VCALENDAR