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DTSTART;TZID=America/Los_Angeles:20260507T120000
DTEND;TZID=America/Los_Angeles:20260507T130000
DTSTAMP:20260311T183306Z
CREATED:20260311T183306Z
LAST-MODIFIED:20260311T183306Z
UID:77858-1778155200-1778158800@svec.org
SUMMARY:Power Distribution in Heterogeneous Integrated Packaging for Data Center Computing
DESCRIPTION:[]Join us for an insightful webinar with Francesco Carobolante\, founder of IoTissimo® LLC and an EPS Distinguished Lecturer\, as he explores the critical challenges and innovative solutions that advanced packaging can provide to address the "Power Wall". With over 30 years of industry experience and a tenure at Intel’s Corporate Strategy Office\, Francesco will delve into the Heterogeneous Integration Roadmap (HIR) perspective on scaling high-power AI processors. This session will analyze how signal BW and energy requirements dictate the options available for architecting the package structure\, including Vertical Power Delivery\, integrated voltage regulators and advanced thermal management techniques. Discover how these architectural shifts are enabling the next generation of data center performance.\nSpeaker(s): Francesco Carobolante\,\nVirtual: https://events.vtools.ieee.org/m/546237
URL:https://svec.org/event/power-distribution-in-heterogeneous-integrated-packaging-for-data-center-computing/
LOCATION:Virtual: https://events.vtools.ieee.org/m/546237
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260512T120000
DTEND;TZID=America/Los_Angeles:20260512T130000
DTSTAMP:20260120T174820Z
CREATED:20260120T174820Z
LAST-MODIFIED:20260120T174820Z
UID:77639-1778587200-1778590800@svec.org
SUMMARY:From Process to Performance: Challenges in uOLED and uLED Electronics Manufacturing
DESCRIPTION:As uOLED and uLED technologies transition from research to high-volume manufacturing\, system performance is increasingly constrained by process variability rather than design intent. Electrical\, thermal\, and mechanical decisions made during manufacturing directly translate into optical non-uniformity\, efficiency loss\, and reliability challenges. Understanding these process-to-performance linkages is critical for building scalable\, high-performance emissive display systems.\nVirtual: https://events.vtools.ieee.org/m/533601
URL:https://svec.org/event/from-process-to-performance-challenges-in-uoled-and-uled-electronics-manufacturing-2/
LOCATION:Virtual: https://events.vtools.ieee.org/m/533601
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260512T170000
DTEND;TZID=America/Los_Angeles:20260512T193000
DTSTAMP:20260427T014956Z
CREATED:20260402T110335Z
LAST-MODIFIED:20260427T014956Z
UID:78240-1778605200-1778614200@svec.org
SUMMARY:The Intelligence of the Machine.. The Rigor of the Road!!
DESCRIPTION:IEEE Event Agenda – Tuesday May 12\, 2026\n🔹 5:00 PM – 5:30 PM\nRegistration\, Refreshments\, Food & Networking (Meet & Greet)\nFeatured Speakers & Sessions\n🔹 5:30 PM – 6:15 PM\nTopic 1: Industry Talk – Standardizing Automotive Firmware for SDVs\nExperts from Mercedes-Benz\, Arm\, and Athos Silicon will discuss the urgent need for a standardized\, secure\, and vendor-agnostic firmware foundation.\nKey focus areas:\n– Overcoming fragmented firmware ecosystems\n– UEFI as a scalable automotive standard\n– Enabling functional safety\, cybersecurity\, and interoperability\n– Supporting chiplet-based and next-gen ADAS architectures\nSpeakers:\n– François Piednoël – (https://www.linkedin.com/in/francoispiednoel/)\n– Sachin Athanikar – (https://www.linkedin.com/in/sachin-athanikar-18ba5914/)\n– Dong Wei (https://www.linkedin.com/in/dongweimba/)\n🔹 6:15 PM – 6:45 PM\nTopic 2: Academic Keynote – Safe Embodied AI: From Theory to Deployment\nProf. Ding Zhao (Carnegie Mellon University)\nTopics include:\n– Rare-event safety in autonomous systems\n– Safe reinforcement and imitation learning\n– Generalizable and adaptive AI safety\n– Future of trustworthy embodied AI at scale\nSpeaker:\n– Ding Zhao – (https://www.linkedin.com/in/ding-zhao-01130730/)\n🔹 6:45 PM – 7:15 PM\nTopic 3: Industry Talk – Static Safety Is Dead: Continuous Risk & Compliance for SDVs\nAkshay Chalana (CEO & Co-founder\, Saphira AI)\nModern vehicles evolve continuously through software updates\, AI-driven functionality\, and increasing connectivity—yet safety and cybersecurity practices remain largely static.\nThis talk explores:\n– What breaks when traditional safety assumptions no longer hold\n– Real-world ADAS/autonomy failure propagation: dataset bias\, requirement drift\, and system boundary ambiguity\n– Cross-domain challenges between safety and cybersecurity\n– A new model for continuous\, system-aware risk assessment and compliance\n– Treating compliance artifacts as live infrastructure integrated into development pipelines\nThis session provides a practical path to maintaining certification-grade rigor while operating at software velocity.\nSpeaker:\n– Akshay Chalana – (https://www.linkedin.com/in/akshaychalana/)\n🔹 7:15 PM – 7:30 PM\nQ&A and open discussion – Aditi Ramadwar\nAbout This Technical Forum\nThis technical forum brings together OEMs\, Tier-1 suppliers\, semiconductor leaders\, researchers\, and innovators to address the challenge of fragmentation and define a unified\, future-ready mobility stack.\nWho Should Attend:\n– Automotive engineers and architects\n– Safety and cybersecurity specialists\n– Semiconductor and embedded systems professionals\n– Researchers in autonomous vehicles and AI safety\n– Technical decision-makers from OEMs and suppliers\n– Students in Automotive\, Compute\, Mechanical & Electrical Engineering\nWe would be delighted if you could join us and participate in shaping the future of intelligent transportation.\nSpeaker(s): Francois\, Wei \, Sachin\, Zhao\, Akshay\nSEMI\, 673 S Milpitas Blvd\, Milpitas\, California\, United States\, 95035
URL:https://svec.org/event/the-intelligence-of-the-machine-the-rigor-of-the-road/
LOCATION:SEMI\, 673 S Milpitas Blvd\, Milpitas\, California\, United States\, 95035
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/04/IEEE-VTS_260512_-speaker_final-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260517T170000
DTEND;TZID=America/Los_Angeles:20260518T180000
DTSTAMP:20260206T094815Z
CREATED:20260206T094815Z
LAST-MODIFIED:20260206T094815Z
UID:77706-1779037200-1779127200@svec.org
SUMMARY:Spring Speaker Series 3
DESCRIPTION:Continuation of Speaker Series at Stanford IEEE.\nStanford\, California\, United States\, 94305
URL:https://svec.org/event/spring-speaker-series-3/
LOCATION:Stanford\, California\, United States\, 94305
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260518T183000
DTEND;TZID=-07:00:20260518T203000
DTSTAMP:20260421T210324Z
CREATED:20260421T210324Z
LAST-MODIFIED:20260421T210324Z
UID:78274-1779129000-1779136200@svec.org
SUMMARY:Closing the Loop: Using Comp Vision to Auto PCB E-Waste Sorting (Student Proj)
DESCRIPTION:**TALK LOGISTICS:**\nMonday\, May 18\, 2026\n(remote speaker\, audience can be either in person or remote on Zoom. Please RSVP and indicate if you will be local or remote) \n6:30 registration\, food sponsored by Neo4j\, networking.\n7:00 SFbayACM upcoming events\, introduce the speaker\n7:10 to 8:15 or 8:30 based on Q and A – presentation \nZoom link:\n(updated 2 days before the event)\nYouTube:\n(updated 2 days before the event) \nSFbayACM will support a local audience at VRP in Mountain View \n.\n**TALK DESCRIPTION:**\nElectronic waste is one of the fastest-growing waste streams in the world\, yet most recycling processes destroy valuable components through industrial shredding. This talk walks through our project building a low-cost\, AI-powered system that identifies and physically sorts reusable components from discarded printed circuit boards (PCBs) — recovering more value at the component level rather than treating boards as bulk scrap. \nA key advantage of our system is cost. Our full build came in at roughly $350\, compared to approximately $5\,000–$6\,000 for a tumbler-based solution — which only recovers lower-value bulk material — and $20\,000+ for a commercial pick-and-place system. \n**Proposed Talk Structure:**\n**1. The Problem** — Scale of PCB e-waste globally and in the Bay Area\, why industrial shredding leaves recoverable value on the table\, and the circular economy opportunity at the component level. \n**2. Technical Approach** — Dataset construction: merging FPIC and Dataset Ninja (~6\,000+ annotated images\, 18 component classes). Model selection: YOLOv11 instance segmentation and why it fits a centroid-based picking system. Training pipeline challenges — class mapping inconsistencies across merged datasets. Results: ~91% mAP across component classes. \n**3. Mechanical Design** — Gantry hardware selection and why a repurposed CR10 3D printer frame made sense. Stepper motor control and coordinate mapping from vision output to physical space. Tradeoffs in the mechanical design — precision vs. cost vs. complexity. \n**4. The Physical System in Action** — Integrating vision model output with the gantry. Video walkthrough of end-to-end component sorting. \n**5. Lessons Learned & Broader Implications** — What broke\, what surprised us\, and what we’d do differently. Potential applications — PCB recyclers\, repair shops\, maker spaces. Where AI fits in sustainable hardware reuse pipelines. \n.\n**SPEAKER’s BIO:**\n**Vighnesh is a junior at Archbishop Mitty High School in San Jose\,** California. He recently competed in his first science fair\, the Synopsys Silicon Valley Science & Technology Championship\, where he and his teammates placed 2nd in the engineering category. His interests span computer vision\, robotics\, and AI\, and he has experience as a junior developer working with TypeScript\, React\, and SQL. He is also a member of his school’s FRC robotics team. \n**Lalit is a junior at Archbishop Mitty High School** specializing in computer vision\, robotics\, and embedded systems\, with hands-on experience spanning Arduino and Raspberry Pi integration\, YOLOv11-based object detection\, and competitive robotics programming in C++. He serves as the lead programmer for his school’s VEX Robotics team and co-president of the Data Science Club\, where he has developed expertise in autonomous systems and real-time control. Along with Vighnesh and Vrishank\, he competed in his first science fair\, the Synopsys Silicon Valley Science & Technology Championship\, where they placed 2nd in the engineering category. \n**Vrishank is a junior at Archbishop Mitty High School in San Jose\,** California. He conducted research at UC Santa Cruz’s COSMOS program in photonics\, working on SPR biosensing and Fresnel lens optimization for solar sails. He competed at the Synopsys Silicon Valley Science & Technology Championship\, where his team placed 2nd in the engineering category with an automated e-waste sorting system. He developed a CAR-T cell therapy manufacturing QC system for the BioHESC bioengineering competition\, where his team placed 1st. His other projects include high voltage electronics such as nixie tube clocks and flyback transformer circuits. His interests are in electrical engineering\, photonics\, and semiconductors\, and he has experience in FRC and FLL robotics.
URL:https://svec.org/event/closing-the-loop-using-comp-vision-to-auto-pcb-e-waste-sorting-student-proj/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/04/1024x576-V9efqx.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260518T183000
DTEND;TZID=-07:00:20260518T203000
DTSTAMP:20260421T210324Z
CREATED:20260421T210324Z
LAST-MODIFIED:20260421T210324Z
UID:78275-1779129000-1779136200@svec.org
SUMMARY:Closing the Loop: Using Comp Vision to Auto PCB E-Waste Sorting (Student Proj)
DESCRIPTION:**TALK LOGISTICS:**\nMonday\, May 18\, 2026\n(remote speaker\, audience can be either in person or remote on Zoom. Please RSVP and indicate if you will be local or remote) \n6:30 registration\, food sponsored by Neo4j\, networking.\n7:00 SFbayACM upcoming events\, introduce the speaker\n7:10 to 8:15 or 8:30 based on Q and A – presentation \nZoom link:\n(updated 2 days before the event)\nYouTube:\n(updated 2 days before the event) \nSFbayACM will support a local audience at VRP in Mountain View \n.\n**TALK DESCRIPTION:**\nElectronic waste is one of the fastest-growing waste streams in the world\, yet most recycling processes destroy valuable components through industrial shredding. This talk walks through our project building a low-cost\, AI-powered system that identifies and physically sorts reusable components from discarded printed circuit boards (PCBs) — recovering more value at the component level rather than treating boards as bulk scrap. \nA key advantage of our system is cost. Our full build came in at roughly $350\, compared to approximately $5\,000–$6\,000 for a tumbler-based solution — which only recovers lower-value bulk material — and $20\,000+ for a commercial pick-and-place system. \n**Proposed Talk Structure:**\n**1. The Problem** — Scale of PCB e-waste globally and in the Bay Area\, why industrial shredding leaves recoverable value on the table\, and the circular economy opportunity at the component level. \n**2. Technical Approach** — Dataset construction: merging FPIC and Dataset Ninja (~6\,000+ annotated images\, 18 component classes). Model selection: YOLOv11 instance segmentation and why it fits a centroid-based picking system. Training pipeline challenges — class mapping inconsistencies across merged datasets. Results: ~91% mAP across component classes. \n**3. Mechanical Design** — Gantry hardware selection and why a repurposed CR10 3D printer frame made sense. Stepper motor control and coordinate mapping from vision output to physical space. Tradeoffs in the mechanical design — precision vs. cost vs. complexity. \n**4. The Physical System in Action** — Integrating vision model output with the gantry. Video walkthrough of end-to-end component sorting. \n**5. Lessons Learned & Broader Implications** — What broke\, what surprised us\, and what we’d do differently. Potential applications — PCB recyclers\, repair shops\, maker spaces. Where AI fits in sustainable hardware reuse pipelines. \n.\n**SPEAKER’s BIO:**\n**Vighnesh is a junior at Archbishop Mitty High School in San Jose\,** California. He recently competed in his first science fair\, the Synopsys Silicon Valley Science & Technology Championship\, where he and his teammates placed 2nd in the engineering category. His interests span computer vision\, robotics\, and AI\, and he has experience as a junior developer working with TypeScript\, React\, and SQL. He is also a member of his school’s FRC robotics team. \n**Lalit is a junior at Archbishop Mitty High School** specializing in computer vision\, robotics\, and embedded systems\, with hands-on experience spanning Arduino and Raspberry Pi integration\, YOLOv11-based object detection\, and competitive robotics programming in C++. He serves as the lead programmer for his school’s VEX Robotics team and co-president of the Data Science Club\, where he has developed expertise in autonomous systems and real-time control. Along with Vighnesh and Vrishank\, he competed in his first science fair\, the Synopsys Silicon Valley Science & Technology Championship\, where they placed 2nd in the engineering category. \n**Vrishank is a junior at Archbishop Mitty High School in San Jose\,** California. He conducted research at UC Santa Cruz’s COSMOS program in photonics\, working on SPR biosensing and Fresnel lens optimization for solar sails. He competed at the Synopsys Silicon Valley Science & Technology Championship\, where his team placed 2nd in the engineering category with an automated e-waste sorting system. He developed a CAR-T cell therapy manufacturing QC system for the BioHESC bioengineering competition\, where his team placed 1st. His other projects include high voltage electronics such as nixie tube clocks and flyback transformer circuits. His interests are in electrical engineering\, photonics\, and semiconductors\, and he has experience in FRC and FLL robotics.
URL:https://svec.org/event/closing-the-loop-using-comp-vision-to-auto-pcb-e-waste-sorting-student-proj-2/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/04/1024x576-V9efqx.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260519T080000
DTEND;TZID=America/Los_Angeles:20260520T170000
DTSTAMP:20260206T094815Z
CREATED:20260206T094815Z
LAST-MODIFIED:20260206T094815Z
UID:77708-1779177600-1779296400@svec.org
SUMMARY:Third Annual IEEE Build-Up Substrate Symposium
DESCRIPTION:[]\n(More information will be added in early March. General Registration should open around March 1st. Sponsors may register at the link below.)\nWe are living in the era of heterogeneous integration driven by fast\, efficient and big data computing resources at our fingertips. The mega-monolithic silicon chip is a thing of the past\, replaced with 3D heterogeneous integration of chiplets onto a platform made of an organic build-up substrate. Volume manufacturers of build-up substrates are entirely based in Asia\, leaving a desert in the US. Volume build-up substrates used by major IDMs are manufactured in Asian countries including Taiwan\, Japan and China.\nHowever\, there are multiple activities starting up in the US\, and this is why a gathering of the US players is important. This symposium is geared for all those involved in the supply chain of build-up substrates in the US\, as well as users. This Symposium is an opportunity for all build-up substrate players to meet\, network and cohesively work with funding agencies who will be invited to this symposium to focus on onshoring build-up substrate production and utilization.\nSamsung\, San Jose\, California\, United States
URL:https://svec.org/event/third-annual-ieee-build-up-substrate-symposium/
LOCATION:Samsung\, San Jose\, CA\, United States
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260519T090000
DTEND;TZID=America/Los_Angeles:20260520T170000
DTSTAMP:20260304T174831Z
CREATED:20260304T174831Z
LAST-MODIFIED:20260304T174831Z
UID:77832-1779181200-1779296400@svec.org
SUMMARY:IEEE Build-Up Substrate Symposium (BUSS)
DESCRIPTION:We are living in the era of heterogeneous integration driven by fast\, efficient and big data computing resources at our fingertips. The mega-monolithic silicon chip is a thing of the past\, replaced with 3D heterogeneous integration of chiplets onto a platform made of an organic build-up substrate. Volume manufacturers of build-up substrates are entirely based in Asia\, leaving a desert in the US. Volume build-up substrates used by major IDMs are manufactured in Asian countries including Taiwan\, Japan and China.\nHowever\, there are multiple activities starting up in the US\, and this is why a gathering of the US players is important. This symposium is geared for all those involved in the supply chain of build-up substrates in the US\, as well as users. As the US Congress debates H.R. 3249\, the Protecting Circuit Boards and Substrates (PCBS) Act\, this Symposium is an opportunity for all build-up substrate players to meet\, network and cohesively work with funding agencies who will be invited to this symposium to focus on onshoring build-up substrate production and utilization.\nlocation to be announced\, Milpitas\, California\, United States\, Virtual: https://events.vtools.ieee.org/m/544352
URL:https://svec.org/event/ieee-build-up-substrate-symposium-buss-2/
LOCATION:location to be announced\, Milpitas\, California\, United States\, Virtual: https://events.vtools.ieee.org/m/544352
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20260525T210000
DTEND;TZID=America/New_York:20260526T170000
DTSTAMP:20260226T173312Z
CREATED:20260226T173312Z
LAST-MODIFIED:20260226T173312Z
UID:77809-1779742800-1779814800@svec.org
SUMMARY:IEEE Canada Blockchain Forum 2026 (4th edition)
DESCRIPTION:The IEEE Blockchain Forum is returning for the fourth time as part of (https://www.torontotechweek.com/). The goal of this compact one-day event is to congregate BUIDLers\, researchers\, academics\, and engineers building blockchain protocols\, infrastructure\, and decentralized software applications.\nNote: (https://events.vtools.ieee.org/m/469545) counted with 200 participants and speakers from JP Morgan\, the Bank of Canada\, Mastercard\, the Ethereum Enterprise Alliance\, EY\, Starknet\, among others.\n[]\nCo-sponsored by: Government of Ontario\nAgenda:\nAgenda TBC\nOntario Investment and Trade Centre\, 250 Yonge Street\, 35th Floor\, Toronto\, Ontario\, Canada\, M5B 2L7
URL:https://svec.org/event/ieee-canada-blockchain-forum-2026-4th-edition/
LOCATION:Ontario Investment and Trade Centre\, 250 Yonge Street\, 35th Floor\, Toronto\, Ontario\, Canada\, M5B 2L7
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260527T190000
DTEND;TZID=-07:00:20260527T210000
DTSTAMP:20260425T210424Z
CREATED:20260425T210424Z
LAST-MODIFIED:20260425T210424Z
UID:78281-1779908400-1779915600@svec.org
SUMMARY:Latest & Unique Tech Innovations from the 2026 Consumer Electronics Show (CES) 
DESCRIPTION:LOCATION ADDRESS (Hybrid\, in person or by zoom\, you choose)\nValley Research Park\n319 North Bernardo Avenue\nMountain View\, CA CA 93043\nIf you want to join remotely\, you can submit questions via Zoom Q&A. The zoom link:\n[https://acm-org.zoom.us/](https://acm-org.zoom.us/j/99320216248?pwd=hmIZXJbNiS0F4hrJerx0ffnI8rbYOr.1)\nJoin via YouTube:\nhttps://youtube.com/live/sJ38lsfLfeU \nAGENDA\n6:30 Door opens\, SFBAY ACM 69 anniversary Cake and networking (we invite honor system contributions)\n**7:00** SFBay ACM 2025 Slate of board members and annual election\, upcoming events.\n7:15 Speaker presents\n8:25- 8:40 finish\, depending on Q&A \nJoin SF Bay ACM Chapter for an insightful discussion on: \nAbstract\nThis is a summary of the latest and unique tech innovations from the **2026 Consumer Electronics Show (CES)** in Las Vegas. CES’s focus has expanded beyond consumer electronic devices to many categories including wearables\, smart homes\, robotics\, drones\, medical and healthcare devices\, etc. \nSpeaker Bio:\n**Avery Lu is one of the leaders in the Valley in tech business development\, and is current Chair of the IEEE Santa Clara Valley Section**.\nAs Partner & Head of Business Development\, Investments for Aventurine Capital Group\, LLC **([www.aventurine.com](http://www.aventurine.com/))**\, Avery Lu leverages his\n30+ year’s experience as a high-tech business executive in both large corporations and startups. He works directly with\npartners in venture capital\, universities and startups as well as scientists to identify high value intellectual property for\ninvestment and commercialization. Avery is also Senior Director of Program Development and Interest Groups at the\nGlobal Semiconductor Alliance (GSA) **([www.gsaglobal.org](http://www.gsaglobal.org/))**\, a global platform “Where Leaders Meet” to establish an efficient\, profitable\, and\nsustainable high technology global ecosystem encompassing semiconductors\, software\, solutions\, systems\, and services. \nHe has previously co-founded 3 startups; Palo Alto Scientific (AI sports analytics/ wearables/IoT)\, ActionSpot Startup Studio\n(venture studio & co-working space) and WBGlobalSemi (SiC power management solutions). Early in his career\, Avery held\nvarious senior level roles in Business Development\, Segment Marketing\, Product Marketing\, Global Account Management\nand Field Applications Engineering at NXP Semiconductor\, Infineon Technologies\, Toshiba Semiconductor\, Winbond Electronics\,\nAmerican Microsystems Incorporated\, Cypress Semiconductor\, Viewlogic Systems and Xilinx. \nAvery is a Senior Member of IEEE (Institute of Electrical & Electronics Engineers) and Professional Member of IEEE Eta\nKappa Nu Honor Society who is the current Chair of IEEE Santa Clara Valley (SCV) Section in Silicon Valley\, a former\n2015-2016 Chair of IEEE SCV Consumer Technology Society Chapter and an Executive Committee Member of IEEE SCV\nStartup Special Interest Group. Since 2011\, he has served on the Board of Directors of CASPA (Chinese American\nSemiconductor Professional Association)\, and has served on the Advisory Board of the Center for Innovation and\nEntrepreneurship at his alma mater\, Santa Clara University\, where he earned his B.S. in Electrical Engineering.\n[www.linkedin.com/in/averylu](http://www.linkedin.com/in/averylu)\n— \nValley Research Park is a coworking research campus of 104\,000 square feet hosting 30+ life science and technology companies. VRP has over 100 dry labs\, wet labs\, and high power labs sized from 125-15\,000 square feet. VRP manages all of the traditional office elements: break rooms\, conference rooms\, outdoor dining spaces\, and recreational spaces. \nAs a plug-and-play lab space\, once companies have secured their next milestone and are ready to expand\, VRP has 100+ labs ready to expand into.\nhttps://www.valleyresearchpark.com/
URL:https://svec.org/event/latest-unique-tech-innovations-from-the-2026-consumer-electronics-show-ces/
LOCATION:Valley Research Park\, 319 N Bernardo Ave\, Mountain View\, CA\, 94043\, United States
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/04/1024x576-hVql9B.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=-07:00:20260529T130000
DTEND;TZID=-07:00:20260529T170000
DTSTAMP:20260503T213310Z
CREATED:20260503T213310Z
LAST-MODIFIED:20260503T213310Z
UID:78368-1780059600-1780074000@svec.org
SUMMARY:Internet Day SF 2026
DESCRIPTION:The goal of **Internet Day SF** is to provide training and thought leadership around any and all aspects of the Internet. \n[https://internetdaysf.org/](https://internetdaysf.org/) \n**This time\, we are virtual only.** We will go live with the material on May 29th. \nThis event is a partnership between the Internet Society San Francisco and SF Bay ACM. \n**Call for Presenters** \nWe are looking for both training and thought leadership presentations in support of the Internet. \nRequirements\, shared requirements for both training and thought leadership: \nSend following to Ronald Petty (DM here):\n* Title and Abstract (approval required)\n* Provide short bio of yourself\, and your email address (to sync later) \n* Speaker(s) **must live and work Bay area** (if you want to present and don’t live here\, we can guide you to related opportunities)\n* **Ability to produce and share video by May 20th** (audio matters to!)\n* Videos **must be under 30 minutes total** (shorter better\, we like things to the point!)\n* **Content must be open source (tools and techniques) and / or public (e.g. regulations)**\n* **No advertising allowed** (unless you are sponsor – requires approval) \nFurther requirements\, **if technical talk**: \n* You **must share a single document** that has all the steps to replicate (markdown is ideal and preferred)\, in addition to the recording. We know not all “devices” might be readily available (aka quantum computers\, but if you have the steps you might try one day!) This is required by 20th as well. \nFurther requirements\, **if thought leadership**: \n* If you are presenting on things like regulations\, you must **provide the links in advance** so others can read about them before the event (aka do their homework!). This is required by 20th as well. \nWe are open to all levels of talks. For example\, just learned a new technique in class to packet sniff\, share it. Want to show people how to be safer on some social application\, please do! Internet of things with AI! We are for it! \nIf you have any questions please DM me. Thank you for your time! \nRonald Petty\nChair – SF Bay ACM
URL:https://svec.org/event/internet-day-sf-2026/
LOCATION:Online event
ATTACH;FMTTYPE=image/jpeg:https://svec.org/wp-content/uploads/2026/05/1024x576-72GTDE.jpg
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