Chapter Open House and talk on AI Infrastructure

Join us for a talk on how SmartNICs and RDMA Power AI in the Cloud, and get insights into the state of the Chapter.
To understand the network requirements of AI, we must first address the CPU bottlenecks of traditional general-purpose networking. This talk begins by analyzing why standard TCP/IP processing limits performance and introduces the concept of "Kernel Bypass" and the role of SmartNICs in offloading network processing from the host CPU. We will explore why modern distributed systems have moved toward hardware offloads (like RDMA) to achieve the high throughput and low latency required for accelerator-to-accelerator communication. We will also discuss the specific challenges of running lossless transport protocols over lossy Ethernet, where congestion and packet drops can cause severe performance degradation ("tail latency") in training clusters. The session concludes by analyzing the architectural design patterns required to optimize flow control and ensure reliable delivery in massive hyperscale environments.
This event features a leading industry expert from Google addressing this important topic, followed by updates on the state of our chapter from the IEEE CIS SCV Chair.
🎤 Talk 1
The Infrastructure of AI: How SmartNICs and RDMA Power the Cloud
Speaker: Sujithra Periasamy, Google
🎤 Talk 2
State of the Chapter
Speaker: Dr. Vishnu S. Pendyala, Chair, IEEE CIS Santa Clara Valley Chapter
Co-sponsored by: Vishnu S. Pendyala, San Jose State University
Speaker(s): Dewank, Dr. Vishnu S Pendyala
Room: MLK Room 225, Dr. Martin Luther King, Jr. Library (SJSU), 150 E San Fernando St San Jose, California 95112, San Jose, California, United States, Virtual: https://events.vtools.ieee.org/m/537154