Digital Lithography: Addressing Scaling Challenges in Advanced Packaging

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Requirements on the high-performance compute (HPC) systems from AI workloads necessitates transition to larger package sizes with 2.5D to 3.5D integration and density scaling at every level in the stack. Several competing packaging architectures are emerging to solve the compute and power efficiency challenge presented by AI workloads. Each presents unique lithography challenges such as >100×100 field size, large chip placement deviations, fine lines and tight overlay warped substrates. The conventional lithography tools are incapable of meeting all the requirements to achieve scaling.
The talk will preview Applied Materials’ Digital Lithography Technology (DLT) which enables highest resolution at production throughputs while ensuring CD uniformity and overlay accuracy across the entire panel.
Speaker(s): Niranjan Khasgiwale,
Virtual: https://events.vtools.ieee.org/m/502777