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Rethinking Chip Design to deliver Faster, Smarter, More Compact Solutions

Bldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road, EAG Labs, 810 Kifer Road, Sunnyvale, California, California, United States, 95051

Rethinking Chip Design to deliver Faster, Smarter, More Compact Solutions [] Abstract: CDimension is rethinking chip design from the ground up, delivering solutions that are faster, smarter, and more compact. We’re moving beyond the limitations of traditional technology. Our foundational innovations in advanced materials and semiconductor integration unlock unprecedented gains in performance, efficiency, and scalability […]

AI-Enhanced Multimodal Approaches for Electronics Metrology and Failure Analysis

Virtual: https://events.vtools.ieee.org/m/498529

The rapid growth of 3D advanced packaging introduces new challenges in inspection and failure analysis, where complex structures such as microbumps, redistribution layers (RDLs), and through-silicon vias (TSVs) demand reliable non-destructive testing (NDT). Conventional approaches, including Scanning Acoustic Microscopy (SAM) and X-ray imaging, are limited by noise, resolution, and defect visibility, creating barriers for reproducible […]

SVEC Open House – Save the Date – November 18, 2025 5:00PM – 8:30PM

Save the Date for the 2025 Open House The Open House event is offers a great opportunity to recognize our member organizations and promote their programs and events, This event features a prominent speaker with a n important technology topic and offers refreshments with networking time for attendees to meet other Silicon Valley engineers. Stay […]

IEEE Symposium on Reliability for Electronics and Photonics Packaging

Milpitas, California, United States, Virtual: https://events.vtools.ieee.org/m/495693

[] This symposium will focus on quantified reliability, accelerated testing and probabilistic assessments of the useful lifetime of electronic, photonic, MEMS and MOEMS materials, assemblies, packages and systems in electronics and photonics packaging. This includes failure modes, mechanisms, testing schemes, accelerated testing, stress levels, and environmental stresses. Visit our website for details, for our Advance […]

Modernizing Power System Design with IEC 61850: Breaking Free from Hardware Constraints

Zio Fraedo’s, 611 Gregory Lane, Pleasant Hill, California, United States, 94523

The power industry is under pressure to rapidly expand infrastructure to meet growing demands from both consumers and producers. But sticking to traditional design and construction methods may no longer be enough. One of the biggest bottlenecks? Hardware dependencies—like waiting on control wiring or specific components—that delay commissioning and inflate project timelines. This presentation explores […]

Characterization and Application of a New Chip-Level Air Pump

Virtual: https://events.vtools.ieee.org/m/500418

[]Trends in consumer goods are leaning towards thinner, more compact products with higher performance than their predecessors. Today’s consumer wants lightweight, portable, battery-operated gear that is powerful enough to satisfy their needs for speed and ease of use. One of the biggest challenges facing product design is thermal management. Case temperature limits for products that […]

AI for Thermal Management of Electronic Systems: A Pathway to Digital Twins

Virtual: https://events.vtools.ieee.org/m/504510

[]The rapid rise in power density and complexity of electronic systems has made thermal management a critical challenge for ensuring reliability, performance, and sustainability. Artificial Intelligence (AI) offers transformative opportunities to address this challenge by enabling data-driven modeling, optimization, and predictive control of cooling systems. By integrating AI with experimental and physics-based approaches, adaptive models […]

Digital Lithography: Addressing Scaling Challenges in Advanced Packaging

Virtual: https://events.vtools.ieee.org/m/502777

[] Requirements on the high-performance compute (HPC) systems from AI workloads necessitates transition to larger package sizes with 2.5D to 3.5D integration and density scaling at every level in the stack. Several competing packaging architectures are emerging to solve the compute and power efficiency challenge presented by AI workloads. Each presents unique lithography challenges such […]

Taming Tech Debt for Platform Reliability

Valley Research Park 319 N Bernardo Ave, Mountain View, CA, United States

LOCATION ADDRESS (Hybrid, in person or by zoom, you choose) Valley Research Park 319 North Bernardo Avenue Mountain View, CA CA 93043 Don't use the front door. When facing the front door, turn right along the front of the building. Turn left around the building corner. The 2nd door should be open and have a […]

IEEE/EPS Hybrid Bonding Symposium

SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas, California, United States, Virtual: https://events.vtools.ieee.org/m/495346

[] Hybrid Bonding has emerged as the technology of choice in the semiconductor industry for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device performance, it will become widely adopted for a broad range of high-performance semiconductor devices in the years to come. The success of Hybrid Bonding technology for high-volume manufacturing depends critically […]