Got a Lot of Chip Designin’ to Do
Room: 225, Bldg: Heafey, Santa Clara University, Santa Clara, California, United States, Virtual: https://events.vtools.ieee.org/m/477704Chiplets are now the standard way to design chips at leading-edge nodes for applications such as AI and high-performance computing. Obvious challenges include the new stage of heterogeneous integration, the new bus that connects the chiplets, and the new advanced packages that hold it all together. No more afterthoughts; packaging, test, integration, and manufacturing must […]